1. Field of the Invention
The present invention relates to a field of microprocessors and more particularly, to a memory management unit utilizing address translation look-aside buffers.
2. Prior Art
The use of a computer system, having a central processing unit (CPU) and an associated memory for storing instructions and/or data is well known in the prior art. The memory may be comprised of a variety of memory devices, such as a read-only memory (ROM), random-access memory (RAM), and/or disk storage device. Typically, a data bus and an address bus couple the CPU to its associated memory or memories. An addressing signal is provided onto the address bus by the CPU for addressing a location within the memory device. Once the address location has been established, then data is either written into or read from the memory by utilizing the data bus. In some instances, the address and data are multiplexed on the same bus lines. In the simplest of computers, the CPU provides the actual physical address of the memory location which is to be accessed.
However, as requirements for additional memory increased, virtual memory systems were devised to provide more addressable memory than that which is physically addressable by the CPU. In a typical virtual memory system, the processor, such as the CPU, generates a virtual address. Then, some form of a memory management unit/system is utilized to translate the virtual address to the physical address. In one such scheme, blocks of physical memory locations are arranged into pages and these pages are mapped into a table or a directory. The virtual address then selects the proper page by accessing the page map or table and the applicable page selects the physical address in memory corresponding to the virtual address. Various virtual addressing techniques are known in the prior art for accessing not only internal memory but also the external memory, as well as any type of cache memory.
With most virtual address systems, some form of address translation is needed to convert the virtual address to the corresponding physical address. Because such address translation takes a certain finite amount of time to translate the virtual address to the physical address, address translation may limit the speed of the processor in executing a certain instruction. This limitation in speed is noticeable in high-speed microprocessor devices currently being implemented, especially where multiple clock cycles are needed to provide the address translation. Where the microprocessor is on a single integrated circuit chip, the size limitation also becomes a significant constraint.
Additionally, where the microprocessor has the capability of performing multi-tasking (i.e. process multiple number of independent tasks), and wherein such multi-tasking is transparent to the user, it is essential that the processor has the capability of protecting certain areas of memory from unauthorized access. For example, it is undesirable for a certain section of memory being allocated to a first user being accessed by a second user. Some form of protection checking is required in order that a multi-tasking system provides the appropriate protection from improper access. In many instances status bits are used to determine which requested access is proper.
More recently, microprocessors have devised schemes of utilizing cache memory to translate the virtual address to physical address. These cache translators termed address translation units operate to provide a physical address without translation, if the corresponding virtual address is located within the translation unit. These translation units utilize cache memory such that the more recently used addresses are stored in the memory. If the virtual address is not located in the cache memory, then the extended technique of translating the virtual address to its physical address is invoked. Where multi-tasking processors are utilized, the prior art systems typically translate the virtual address, either through the cache or through the extended technique, and then, the access codes are checked to determine if that given physical memory location may be accessed for the operation being executed and/or the user requesting access. However, such serial processing will take longer time, usually multiple clock cycles, to perform.
It is appreciated then that a reduction in the time period for performing such address translation, as well as determining the access right, will reduce the overall time period for executing a given instruction within a microprocessor.